1. Field of the Invention
This invention relates to semiconductor memories, particularly to non-volatile memories using variable threshold transistors.
2. Description of the Prior Art
Electrically alterable non-volatile memories may comprise an array of variable threshold transistors, address circuitry to access individual transistors within the array, and sense amplifiers to detect the threshold state of accessed transistors. An electrically alterable non-volatile memory may be a random access memory or an electrically alterable read-only-memory. A random access memory has comparable read and write times for entering and withdrawing information from any word in the memory, whereas an electrically alterable read-only-memory has short read times to any word and much longer write times. In an electrically alterable read-only-memory, information is normally written into the array once and then read out many times.
In an electrically alterable read-only-memory the contents within the array may be altered on a word-by-word basis or the entire contents may be erased to one memory state and selected bits of the memory rewritten to the second memory state on a word by word basis.
One example of an electrically alterable non-volatile memory is described in U.S. Pat. No. 4,160,291 which issued on July 3, 1979, entitled "Pre-Charge Circuitry for an Electrically Alterable Non-Volatile Memory" by P. C. Smith and J. L. Fagan and assigned to the assignee herein. In U.S. Pat. No. 4,160,291, P channel circuitry was used to implement the address row and column decoders as well as the sense amplifier. The voltages required to operate the memory as shown in FIGS. 2A and 2B required voltage swings during read operation of 0 to -25 volts and 0 to -30 volts as shown in FIG. 8.
A random access non-volatile memory was described in U.S. Pat. No. 4,090,258, which issued on May 16, 1978, entitled "MNOS Non-Volatile Memory with Write Cycle Suppression" to J. R. Cricchi and assigned to the assignee herein. In U.S. Pat. No. 4,090,258 two variable threshold transistors were shown to comprise a memory cell each written to the opposite threshold state. During read operation a sense amplifier was coupled to the source of each of the two transistors in the memory cell that was being addressed.
Instead of electrically altering a non-volatile memory, some designs have utilized ultraviolet light to erase the non-volatile transistors to one memory state followed by electrically rewriting selected bits of each word of the memory to the second memory state. One example of an ultraviolet erasable read-only-memory is described in an article entitled "Single-Supply Erasable PROM Saves Power with C-MOS Process" by G. Ramachandran, which appearred in Electronics Magazine, July 6, 1978, pages 106-111. At page 108 in FIG. 3 an address register is shown which uses complementary metal oxide semiconductor circuitry to provide speed and low power. The memory transistor shown in the Figures on page 107 uses a floating silicon gate which holds charge to alter the threshold voltage of the transistor.
The speed from which data can be read out of an array of non-volatile memory transistors depends in part upon the sense amplifier used. Several sense amplifiers have been perfected for use with variable threshold transistors. On such sense amplifier is described in U.S. Pat. No. 4,139,911, which issued on Feb. 13, 1979 entitled "High Speed Sense Circuit for Semiconductor Memories" by F. M. Sciulli and D. W. Williams which is assigned to the assignee herein and which describes a high-speed sensing circuit utilizing all P channel transistors coupled to the source of the memory transistors in the array.
In U.S. Pat. No. 4,170,741 which issued on Oct. 9, 1979, entitled "High Speed CMOS Sense Circuit for Semiconductor Memories" by D. W. Williams and assigned to the assignee herein, a high-speed sense circuit utilizing complementary metal oxide semiconductor transistors is shown coupled to the source of the variable threshold transistors in the memory array.
The typical method for reading data out from an array of metal nitride oxide semiconductor transistors was to set the drain of the transistors to a negative voltage and allow the source of the selected transistor to follow the gate bias voltage by a threshold voltage V.sub.T away. This is normally termed the source follower mode. As the gate-to-source voltage approaches V.sub.T as the source voltage is being pulled down to V.sub.GS equals V.sub.T, less current passes through the transistor which results in discharging the node capacitances slowly.
It is therefore desirable to provide an electrically alterable non-volatile memory which uses CMOS circuitry to reduce the power.
It is further desirable to provide a sense amplifier which responds quickly to the output of selected transistors in a non-volatile memory array.
It is further desirable to provide a sense amplifier which decouples the sense amplifier from the non-volatile memory array after initial sensing.
It is further desirable to operate a non-volatile memory array at reduced voltages during read operation.
It is further desirable to provide an array of metal nitride oxide semiconductor transistors with the selected transistor during read operation having a constant gate-to-source voltage V.sub.GS and operating in the common source mode.
It is further desirable to provide circuitry for writing into an array of metal nitride oxide semiconductor transistors which minimizes the amount of circuitry subjected to high voltages during write operation.